DS1806 digital sextet potentiometer DS1806 022698 1/8 features ? six digitally controlled 64position potentiometers ? 3wire serial port provides for reading and setting each potentiometer ? devices can be cascaded for single processor multi device control ? standard resistance values DS1806010 10k ohm DS1806050 50k ohm DS1806100 100k ohm ? temperature: industrial: 40 c to +85 c pin assignment v cc h1 h2 h3 h4 h5 w5 h6 d in c out w1 w2 l1-3 w3 w4 l4-6 w6 rst clk gnd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DS1806 20pin dip (300 mil) DS1806s 20pin soic (300 mil) DS1806e 20pin tssop (173 mil) see mech. drawings section pin description v cc 3v or 5v supply rst serial port reset input d in serial port data input clk serial port clock input c out cascade data output h1 h6 high end terminal of pot w1 w6 wiper terminal of pot gnd ground l13 low terminal pots 1 thru 3 l46 low terminal pots 4 thru 6 description the DS1806 is a sixchannel digitally controlled solid state linear potentiometer. each potentiometer is com- prised of 63 equiresistive sections as illustrated in the block diagram of figure 1. each potentiometer has three terminals accessible to the user. these include the high side terminals, h x , the wiper terminals, w x , and the lowend terminals, l13 and l46. potentiometers 1 through 3 share the same lowend terminal l13. and likewise, potentiometers 4 through 6 share the lowend terminal l46. each wiper's position is selected via an 8bit register value. communication and control of the device is ac- complished via a 3wire serial port interface. this inter- face in conjunction with a cascade output allows the val- ue of the device wiper settings to be read. for multiple device and single processor environments, the DS1806 can be cascaded or daisy chained. this feature allows a single processor to control multiple de- vices. the DS1806 is available in 10k, 50k and 100k ohm ver- sions and is specified over the industrial temperature range. packages for the device include 20lead dips, soics, and tssops.
DS1806 022698 2/8 operation a block diagram of the device is provided in figure 1. as shown, the DS1806 contains six 64position potentiom- eters whose wiper positions are set by an 8bit value. the DS1806 contains a 48bit i/o shift register which is used to store the respective wiper position data for each of the six potentiometers. each potentiometer has three terminals accessible to the user. these include the high side terminals, h x , the wiper terminals, w x , and the lowend terminals, l13 and l46. potentiometers 1 through 3 share the same lowend terminal l13. and likewise, potentiometers 4 through 6 share the lowend terminal l46. control of the DS1806 is accomplished via a 3wire se- rial communication interface which allows the user to set the wiper position value for each potentiometer. the 3wire serial interface consists of the control signals rst , d in , and clk. on powerup, the wiper positions of each potentiometer are set to the lowend terminal l x (00000000). the rst control signal is used to enable 3wire serial port operation. the rst signal (3wire serial port) is ac- tive when in a high state. any communication intended to change wiper settings must begin with the transition of the rst from the lowstate to the highstate. the clk signal input is used to provide timing synchro- nization for data input and output. wiper position data is loaded into the DS1806 through the d in input terminal. this data is shifted one bit at a time into the 48bit i/o shift register of the part, lsb first. figure 3 provides an illustration of the 48bit shift register. figure 4 provides 3wire serial port protocol and timing diagrams. as shown, the 3wire port is inactive when the rst signal input is low. once rst has transitioned from the low to the high state, the serial port becomes active. when active, data is loaded into the i/o shift reg- ister on the lowtohigh transition of the clk. data is transmitted in order of lsb first. potentiometers are designated from 1 through 6 and the value for poten- tiometer1 will be the first data entered into the shift reg- ister, followed by that of potentiometer2 and so forth. each wiper has an 8bit register which is used for set- ting the position of the wiper on the resistor array. be- cause the DS1806 is a 64position potentiometer, only six bits of information are needed to set wiper position. the remaining two bits of information are used to pro- vide a adon't changeo feature. wiper position is con- trolled by bit positions 0 through 5 of each register. the adon't changeo feature is controlled by bits 6 and 7 of each register. when bits 6 and 7 have value a11 xxxxxxo, wiper position will not change regardless of the states of bits 0 through 5. if bits 6 and 7 are set to any other value, bits 0 through 5 will be used as the new wiper position. the adon't changeo feature allows the user to change the value of any potentiometer of the DS1806 without af- fecting or having to remember the remaining positions of the potentiometer wipers. figure 2 provides the for- mat for a wiper's register. wiper placement for each potentiometer is such that position63 corresponds to the h x terminal of the de- vice while position0 corresponds to the ground termi- nal. for example, to set a potentiometer's wiper position to 15 (decimal), the binary value shifted into the wiper register should be 00001111. this will place the wiper tap at the 15th step above the low end terminal, l x . all communication transactions should provide the total 48 bits of information when writing or reading from the part. this is especially true for applications using all six potentiometers. if a complete set of 48 bits is not trans- mitted to the part, undesired wiper position settings may occur.
DS1806 022698 3/8 DS1806 block diagram figure 1 h6 64to1 multiplexer l46 potentiometer6 w6 h5 64to1 multiplexer potentiometer5 w5 h1 64to1 multiplexer potentiometer1 w1 l13 . . . . . . . . . . . . wiper6 (8 bits) wiper5 (8bits) wiper1 (8bits) 48bit shift register d in rst clk c out 3wire serial interface control logic wiper register configuration figure 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 msb lsb load/no load wiper position value bits 6 and 7 functionality 11 do not load wiper value 10 load wiper value 01 load wiper value 00 load wiper value 48bit i/o shift register figure 3 b0 pot 1 b7 b0 pot 2 b7 b0 pot 3 b7 b0 pot 4 b7 b0 pot 5 b7 b0 pot 6 b7 msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb data entered lsb first, starting with potentiometer1.
DS1806 022698 4/8 3wire serial port timing figure 4 ??? ??? ??? rst clk d in c out lsb pot 1 t cc t ch t rlt t hlt t cdh t dc cascade operation a feature of the DS1806 is the ability to control multiple devices from a single processor. multiple DS1806s can be linked or daisy chained as shown in figure 5. as a data bit is entered into the i/o shift register of the DS1806, a bit will appear at the c out terminal before a maximum delay of 50 nanoseconds. the lsb of poten- tiometer1 will always be the first out of the part at the beginning of a transaction. additionally, the c out termi- nal is always active regardless of the state rst . howev- er, d in and clk inputs are ignored when rst is in the low state. the c out output of the DS1806 can be used to drive the d in input of another DS1806. when cascading multiple devices, the total number of bits transmitted is always 48 multiplied by the total number of DS1806s being cas- caded. an optional feedback resistor can be placed between the c out terminal of the last device and the first DS1806 d in input, which allows the controlling processor to read, as well as, write data, or circularly clock data through the daisy chain. the value of the feedback or isolation resistor should be in the range from 1k w to 10k w . to read data, the reading device configures itself as an input and monitors the state of the d in line, which is driv- en by c out through the isolation resistor. when rst is driven high, bit 48 is present on the c out pin, which is fed back to the input d in pin through the isolation resis- tor. when the clk input transitions low to high, bit 48 is loaded into the first position of the i/o shift register and bit 47 becomes present on c out and d in of the next de- vice. after 48 bits (or 48 times the number of the DS1806s in the daisy chain), the data has shifted com- pletely around and back to its original position. when rst transitions to the low state to end data transfer, the value (the same as before the read occurred) is loaded in the shift register. absolute and relative linearity absolute linearity is defined as the difference between the actual measured output voltage and the expected output voltage. absolute linearity is given in terms of a minimum increment or expected output when the wiper is moved one position. the DS1806 is specified to have an absolute linearity of 0.50 lsb. relative linearity is a measure of error between two ad- jacent wiper position points. the DS1806 is specified to have a relative linearity of 0.25 lsb. typical application configurations figure 6 shows the typical application configuration of the DS1806 as a fixed gain attenuator. in this configura- tion, the DS1806 adjusts the attenuation level of the in- coming signal. variations in wiper resistance are mini- mized by connecting the wiper terminal of the part to a high impedance load. depending on voltage across the wiper, its resistance may vary from 400 ohms to 1000 ohms. note that the resistance r1 in figure 6 should be chosen to be much greater than the wiper re- sistance r w .
DS1806 022698 5/8 cascading multiple devices figure 5 DS1806 #1 DS1806 #2 DS1806 #n c out c out c out d in d in d in isolation resistor for reading register data 1k w 10k w fixed gain attenuator figure 6 + hx lx wx r f r 1 DS1806
DS1806 022698 6/8 absolute maximum ratings* voltage on any pin relative to ground 0.5v to +7.0v operating temperature 40 c to +85 c; industrial storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (-40 c to +85 c) parameter symbol min typ max units notes supply voltage v cc +2.7 5.5 v 1 dc electrical characteristics (40 c to +85 c; v cc = 2.7 to 5.5v) parameter symbol min typ max units notes supply current active i cc 1.3 2 ma input leakage i il 1 +1 m a wiper resistance r w 400 1000 w wiper current i w 1 ma input logic 1 v ih 2.0 v cc +0.5 v 1 input logic 0 v il 0.5 +0.8 +0.6 v 1, 6 logic 1 output @ 2.4 volts i oh 1 ma logic 0 output @ 0.4 volt i ol 4 ma 6 standby current: 3 volts 5 volts i stby 12 20 40 m a m a 9 resistor inputs h x , l x , w x gnd 0.5 v cc +0.5 m a 2 analog resistor characteristics (40 c to +85 c; v cc = 2.7 to 5.5v) parameter symbol min typ max units notes endtoend resistor tolerance 20 +20 % absolute linearity 0.5 +0.5 lsb 7 relative linearity 0.25 +0.25 lsb 8 3 db cutoff frequency i cutoff hz 4 temperature coefficient 650 ppm/ c
DS1806 022698 7/8 capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 5 pf 3 output capacitance c out 7 pf 3 ac electrical characteristics (-40 c to +85 c; v cc = 2.7 to 5.5v) parameter symbol min typ max units notes clock frequency f clk dc 10 mhz 5 width of clk pulse t ch 50 ns 5 data setup time t dc 30 ns 5 data hold time t cdh 0 ns 5 propagation delay time low to high level clock to output t plh 50 ns 5 rst high to clock input high t cc 50 ns 5 rst low from lock input high t hlt 50 ns 5 rst inactive t rlt 125 ns 5 clk rise time, clk fall time t cr 50 ns 5 notes: 1. all voltages are referenced to ground. 2. resistor inputs cannot go below gnd by more than 0.5 volts or above v cc by 0.5 volts in the positive direction. 3. capacitance values apply at 25 c. 4. 3 db cutoff frequency characteristics for the DS1806 depend on potentiometer total resistance: DS1806010; 1 mhz; DS1806050; 200 khz, DS1806100; 100 khz. 5. see figure 4. 6. for v cc = 5v 10% maximum v il = +0.8v. for v cc = 3.0 10% v il = +0.6v. 7. absolute linearity is to used measure expected wiper voltage versus measured wiper voltage as determined by wiper position. the DS1806 is specified to provide an absolute linearity of + 0.5 lsb. 8. relative linearity is used to determine the change in wiper voltage between two adjacent wiper positions. the DS1806 is specified to provide a relative linearity of + 0.25 lsb. 9. standby current levels apply when all inputs are driven to appropriate supply levels.
DS1806 022698 8/8 DS1806 ordering information ordering number package operating temperature version DS1806010 20l dip 40 c to +85 c 10k w DS1806050 20l dip 40 c to +85 c 50k w DS1806100 20l dip 40 c to +85 c 100k w DS1806e010 20l tssop (173 mil) 40 c to +85 c 10k w DS1806e050 20l tssop (173 mil) 40 c to +85 c 50k w DS1806e100 20l tssop (173 mil) 40 c to +85 c 100k w DS1806s010 20l soic (300 mil) 40 c to +85 c 10k w DS1806s050 20l soic (300 mil) 40 c to +85 c 50k w DS1806s100 20l soic (300 mil) 40 c to +85 c 100k w
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